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RM0008
Basic timers (TIM6&TIM7)
Figure 154. Control circuit in normal mode, internal clock divided by 1
CK_INT
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
15.3.4
Debug mode
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 29.16.2: Debug
support for timers, watchdog, bxCAN and I 2 C .
15.4
15.4.1
TIM6&TIM7 registers
Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions.
TIM6&TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARPE
OPM
URS
UDIS
CEN
Reserved
Reserved
rw
rw
rw
rw
rw
Bits 15:8 Reserved, always read as 0
Bit 7 ARPE : Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, always read as 0
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Doc ID 13902 Rev 9
381/995
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